1. Field of the Invention
The present disclosure relates to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
In recent years, researches for a field effect transistor (FET) using a gallium nitride (GaN)-based compound semiconductor material have been actively performed as a power device.
Since a nitride semiconductor material such as GaN can be used for manufacturing various mixed crystals such as aluminum nitride (AlN) and indium nitride (InN), heterojunction can be formed similar to an arsenic semiconductor material such as gallium arsenide (GaAs) in the related art. Particularly, in the heterojunction due to the nitride semiconductor, even in an undoped state, high concentration carriers generated by spontaneous polarization or piezoelectric polarization are generated on an interface of the heterojunction. As a result, in a case where FET is manufactured, the FET is easily formed in a depression type (normally-on type). Accordingly, it is difficult to achieve a characteristic of an enhancement type (normally-off type). However, currently, most devices available in a power electronics market are the normally-off type, and thus, the normally-off type is also strongly necessary for the GaN-based nitride semiconductor device.
As a normally-off type transistor, there is a structure in which a gate formation region is dug to shift a threshold voltage of a gate into a positive value (for example, see Non Patent Literature 1). Further, for example, there is a method in which an FET is manufactured on a (10-12) plane which is a plane orientation of a crystal plane in a substrate made of sapphire and a polarization field is prevented from being generated in a direction of crystal growth of the nitride semiconductor, to thereby realize a normally-off type (for example, see Non Patent Literature 2). Here, a negative sign “−” attached to a mirror index in the plane orientation represents inversion of one index subsequent to the negative sign, for convenience.
Further, as a desirable structure for realizing the normally-off type FET, a junction field effect transistor (JEFT) in which a p-type GaN layer is provided in a gate formation region has been proposed (for example, see Patent Literature 1).
In the JFET, piezoelectric polarization generated on a first heterointerface between a channel layer made of GaN and a barrier layer made of AlGaN is canceled by different piezoelectric polarization generated on a second heterointerface between the barrier layer made of AlGaN and a p-type GaN layer provided thereon. Thus, it is possible to selectively reduce a two-dimensional electron gas (2DEG) immediately under a gate formation region where the p-type GaN layer is formed. Accordingly, the JFET can realize a normally-off characteristic. Further, by using, in a gate electrode, pn junction having a built-in potential larger than that of Schottky contact which is contact between a metal and a semiconductor, it is possible to increase a rising voltage of a gate. Thus, even when a positive gate voltage is applied, it is possible to reduce a leakage current of the gate.